1. Field of the Invention
The present invention relates to MOSFET transistor fabrication and more particularly to a MOSFET transistor and fabrication method wherein a junction is extended to follow an engineered contour in response to a selectively shaped spacer.
2. Description of the Background Art
Within conventional fabrication processes, implanted source-drain regions of the MOSFET transistor are extended to increase immunity of a device to short-channel effects including threshold voltage (Vth) roll-off and drain-induced lowering of barrier voltage. MOSFETs which are fabricated with uniformly doped channels exhibit rapid threshold voltage (Vth) roll-off with reduced gate length Lg. To reduce the short-channel effects as channel depth decreases, processes are being developed for utilizing multiple implantation stages to fabricate a MOSFET transistor with a channel that contains an implanted pocket region. As channel length continues to decrease, these conventional mechanisms are insufficient to stave off short-channel effects. Furthermore, as spacer width is decreased in a scaled device, formation of silicide within a deep source-drain junction may overlap the channel region to create a severe punch-through risk within a subsurface.
Therefore, a need exists for a MOSFET transistor and method of fabrication which reduce short-channel effects. The present invention satisfies that need, as well as others, and overcomes the deficiencies of previously developed solutions.
The present invention describes a MOSFET transistor and associated fabrication method for extending the source-drain regions to follow an engineered profile and to facilitate the formation of a deep silicide layer on the source and drain to reduce the risk of punch-through. The method utilizes the formation of multiple insulation spacers over a gate stack under which a primary implantation has been performed. The two spacers are selectively etched to form an L-shaped spacer adjacent the gate stack with an implantation xe2x80x9ccutoutxe2x80x9d proximal the side of the adjacent gate stack. Implant extensions are performed through the L-shaped spacer which creates a junction profile responsive to the L-shaped spacer and the implantation xe2x80x9ccutoutsxe2x80x9d. It will be appreciated that a stepped junction having pocketed steps may be created within a single deep implantation step as performed through the L-shaped spacer. The method is thereby capable of reducing the number of implantations required for a given stepped profile. The pocketed steps create a transition from a deep implantation under the respective source and drain contacts to a narrow implantation beneath the gate electrode. After implantation, solid-phase epitaxy is preferably performed within a low-temperature anneal process to recrystallize the silicon and to activate the implanted dopants. The L-shaped spacer is subsequently utilized after junction formation to insulate the gate from the source and drain regions such that the contact spacing may be minimized.
By way of example the L-shaped spacer is formed according to the following series of steps. Three spacer layers are deposited over substrate, each layer capable of being selectively etched in relation to the other layers. The majority of the third spacer layer is subsequently removed by etching, wherein the only portions of material that remain are located at the base of the gate stack, which is still covered by the first and second spacer layers. The material from the third deposited layer which remains after etching is referred to as a third spacer. A subsequent etching step is performed to remove portions of the first and second spacer that are not protected by the third spacer. After shaping the first and second spacer layers, the third spacer and a vertical portion of the first spacer are removed. Implantation through the contoured L-shaped spacer results in the formation of a junction having a desired profile. The contoured L-shaped spacer insulates the gate from the source and drain. The contour of the junction provides a deep implantation under the source and drain regions which are capable of supporting a thick silicide layer. The remainder of the MOSFET transistor may be formed utilizing conventional fabrication steps.
An object of the invention is to provide a convenient method for engineering the junction contour within a MOSFET transistor.
Another object of the invention is to engineer a stepped junction contour without the use of additional implantation steps.
Another object of the invention is to provide a MOSFET transistor having a short contact spacing to enhance circuit density.
Another object of the invention is to facilitate source-drain silicide formation to a depth that can exceed the depth of the implanted junction depth below the gate stack.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.